rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a cmos 80 mhz, 10-bit video dac ADV7128 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 functional block diagram i out clock ADV7128 d0 d9 10 fs adjust 10 v aa reference amplifier comp dac data register gnd v ref product highlights 1. fast video refresh rate, 80 mhz. 2. guaranteed monotonic to 10 bits. ten bits of resolution al- lows for implementation of linearization functions such as gamma correction and contrast enhancement. 3. compatible with a wide variety of high resolution color graphics systems including rs-343a/rs-170 and the pro- posed smpte 240m standard for hdtv. 4. combined with a numerically controlled oscillator (ad9955), it forms a complete frequency synthesizer (dds). 5. using the parts reduced power output dac modes, it is ideal for power and cost sensitive communications type applications. general description the ADV7128 (adv ) is a video speed, digital-to-analog con- verter on a single monolithic chip. it consists of a high speed, 10-bit, video d/a converters; a standard ttl input interface; and a high impedance, analog output, current source. the ADV7128 has a 10-bit pixel input port. a single +5 v power supply, an external 1.23 v reference and pixel clock input are and all that are required to make the part operational. the ADV7128 is capable of generating video output signals which are compatible with rs-343a, rs-170 and most pro- posed production system hdtv video standards, including smpte 240m. the ADV7128 is fabricated in a +5 v cmos process. its monolithic cmos construction ensures greater functionality with low power dissipation. the ADV7128 is available in a 28- lead small outline ic (soic). adv is a registered trademark of analog devices, inc. features 80 mhz pipelined operation 10-bit d/a converters rs-343a/rs-170 compatible outputs ttl compatible inputs +5 v cmos monolithic construction 28-pin soic package applications high definition television (hdtv) high resolution color graphics digital radio modulation cae/cad/cam applications image processing instrumentation video signal reconstruction direct digital synthesis (dds) & i/o modulation wireless lan wireless local loop speed grades 80 mhz 50 mhz 30 mhz
rev. 0 C2C ADV7128Cspecifications (v aa = +5 v 6 5%; v ref = +1.235 v; r l = 37.5 v , c l = 10 pf; r set = 560 v . all specifications t min to t max 1 unless otherwise noted.) parameter k version units test conditions/comments static performance resolution 10 bits accuracy integral nonlinearity, inl 1 lsb max differential nonlinearity, dnl 1 lsb max guaranteed monotonic gray scale error 5 % gray scale max max gray scale current = (v ref * 7,969/r set ) ma coding binary digital inputs input high voltage, v inh 2 v min input low voltage, v inl 0.8 v max input current, i in 1 m a max v in = 0.4 v or 2.4 v input capacitance, c in 2 10 pf max analog output gray scale current range 15 ma min 22 ma max output current white level 16.74 ma min typically 17.62 ma 18.50 ma max black level 0 m a min typically 5 m a 50 m a max lsb size 17.28 m a typ output compliance, v oc 0 v min +1.4 v max output impedance, r out 2 100 k w typ output capacitance, c out 2 30 pf max i out = 0 ma voltage reference voltage reference range, v ref 1.14/1.26 v min/v max v ref = 1.235 v for specified performance input current, i vref C5 ma typ power requirements v aa 5 v nom i aa 125 ma max typically 80 ma: 80 mhz parts 100 ma max typically 70 ma: 50 mhz & 35 mhz parts power supply rejection ratio 2 0.5 %/% max typically 0.12%/%: f = 1 khz, comp = 0.1 m f power dissipation 625 mw max typically 400 mw: 80 mhz parts 500 mw max typically 350 mw: 50 mhz & 30 mhz parts dynamic performance glitch impulse 2, 3 50 pv secs typ dac noise 2, 3, 4 200 pv secs typ notes 1 temperature range (t min to t max ); 0 c to +70 c. 2 sample tested at +25 c to ensure compliance. 3 ttl input values are 0 to 3 volts, with input rise/fall times 3 ns, measured between the 10% and 90% points. timing reference points at 50% for inputs and outputs. see timing notes in figure 1. 4 this includes effects due to clock and data feedthrough. specifications subject to change without notice.
ADV7128 rev. 0 C3C timing characteristics 1 (v aa = +5 v 6 5%; v ref = +1.235 v; r l = 37.5 v , c l = 10 pf; r set = 560 v . all specifications t min to t max 2 unless otherwise noted.) parameter 80 mhz version 50 mhz version 30 mhz version units conditions/comments f max 80 50 30 mhz max clock rate t 1 3 6 8 ns min data & control setup time t 2 2 2 2 ns min data & control hold time t 3 12.5 20 33.3 ns min clock cycle time t 4 4 7 9 ns min clock pulse width high time t 5 4 7 9 ns min clock pulse width low time t 6 30 30 30 ns max analog output delay 20 20 20 ns typ t 7 3 3 3 ns max analog output rise/fall time t 8 3 12 15 15 ns typ analog output transition time notes 1 ttl input values are 0 to 3 volts, with input rise/fall times 3 ns, measured between the 10% and 90% points. timing reference points at 50% for inputs and outputs. see timing notes in figure 1. 2 temperature range (t min to t max ): 0 c to +70 c 3 sample tested at +25 c to ensure compliance. specifications subject to change without notice. clock data t 1 t 2 t 3 t 4 t 5 t 8 t 7 t 6 analog outputs (i out ) digital inputs d0?9 notes 1. output delay ( t 6 ) measured from the 50% point of the rising edge of the clock to the 50% point of full-scale transition. 2. transition time ( t 8 ) measured from the 50% point of full-scale transition to within 2% of the final output value. 3. output rise/fall time ( t 7 ) measured between the 10% and 90% points of full-scale transition. figure 1. video input/output timing recommended operating conditions parameter symbol min typ max units power supply v aa 4.75 5.00 5.25 volts ambient operating temperature t a 0 +70 c output load r l 37.5 w reference voltage v ref 1.14 1.235 1.26 volts ordering guide accuracy temperature package model speed dnl inl range option* ADV7128kr80 80 mhz 1 10 c to +70 c r-28 ADV7128kr50 50 mhz 1 10 c to +70 c r-28 ADV7128kr30 30 mhz 1 10 c to +70 c r-28 *r = soic.
ADV7128 rev. 0 C4C absolute maximum ratings * v aa to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7 v voltage on any digital pin . . . . . . gnd C0.5 v to v aa +0.5 v ambient operating temperature (t a ) . . . . . . . . 0 c to +70 c storage temperature (t s ) . . . . . . . . . . . . . . . C65 c to +150 c junction temperature (t j ) . . . . . . . . . . . . . . . . . . . . . +150 c lead temperature (soldering, 10 secs) . . . . . . . . . . . . +300 c vapor phase soldering (2 minutes) . . . . . . . . . . . . . . . +220 c i out to gnd 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to v aa notes * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 analog output short circuit to any power supply or common can be of an indefinite duration. pin configuration 1 2 3 7 28 27 26 22 8 9 10 21 20 19 11 12 18 17 4 5 25 24 6 23 top view (not to scale) 13 14 16 15 ADV7128 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 r set comp gnd gnd clock v aa i out v aa v aa v aa v aa v aa v aa v aa v aa v aa v aa v ref warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADV7128 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. pin function description pin mnemonic function clock clock input (ttl compatible). the rising edge of clock latches the r0Cr9, g0Cg9, b0Cb9, sync and blank pixel and control inputs. it is typically the pixel clock rate of the video system. clock should be driven by a dedicated ttl buffer. d0Cd9 data inputs (ttl compatible). data is latched on the rising edge of clock. d0 is the least significant data bit. unused data inputs should be connected to either the regular pcb power or ground plane. i out current output. this high impedance current source is capable of directly driving a doubly terminated 75 w coaxial cable. r set full-scale adjust control. a resistor (r set ) connected between this pin and gnd, controls the magnitude of the full-scale video signal. note that the ire relationships are maintained, regardless of the full-scale output current. the relationship between r set and the full-scale output current on i out is given by: i out (ma) = 7,969 3 v ref (v)/r set ( w ) comp compensation pin. this is a compensation pin for the internal reference amplifier. a 0.1 m f ceramic capacitor must be connected between comp and v aa . v ref voltage reference input. an external 1.23 v voltage reference must be connected to this pin. the use of an exter- nal resistor divider network is not recommended. a 0.1 m f decoupling ceramic capacitor should be connected be- tween v ref and v aa . v aa analog power supply (5 v 5%). all v aa pins on the ADV7128 must be connected. gnd ground. all gnd pins must be connected.
ADV7128 rev. 0 C5C terminology color video (rgb) this usually refers to the technique of combining the three pri- mary colors of red, green and blue to produce color pictures within the usual spectrum. in rgb monitors, three dacs are required, one for each color. gray scale the discrete levels of video signal between reference black and reference white levels. a 10-bit dac contains 1024 different levels, while an 8-bit dac contains 256. raster scan the most basic method of sweeping a crt one line at a time to generate and display images. reference black level the maximum negative polarity amplitude of the video signal. reference white level the maximum positive polarity amplitude of the video signal. video signal that portion of the composite video signal which varies in gray scale levels between reference white and reference black. also referred to as the picture signal, this is the portion which may be visually observed. circuit description and operation the ADV7128 contains one 10-bit d/a converter, with one in- put channel containing a 10-bit register. also integrated on board the part is a reference amplifier. digital inputs ten bits of data (color information) d0Cd9 are latched into the device on the rising edge of each clock cycle. this data is pre- sented to the 10-bit dac and is then converted to an analog output waveform. see figure 2. clock data analog outputs i out digital inputs d0?9 figure 2. video data input/output all these digital inputs are specified to accept ttl logic levels. clock input the clock input of the ADV7128 is typically the pixel clock rate of the system. it is also known as the dot rate. the dot rate, and hence the required clock frequency, will be determined by the on-screen resolution, according to the following equation: dot rate = (horiz res) (vert res) (refresh rate)/ (retrace factor) horiz res = number of pixels/line. vert res = number of lines/frame. refresh rate = horizontal scan rate. this is the rate at which the screen must be refreshed, typi- cally 60 hz for a noninterlaced system or 30 hz for an interlaced system. retrace factor = total blank time factor. this takes into account that the display is blanked for a certain fraction of the total duration of each frame (e.g., 0.8). if we, therefore, have a graphics system with a 1024 1024 resolution, a noninterlaced 60 hz refresh rate and a retrace fac- tor of 0.8, then: dot rate = 1024 1024 60/0.8 = 78.6 mhz the required clock frequency is thus 78.6 mhz. all video data and control inputs are latched into the ADV7128 on the rising edge of clock, as previously described in the digital inputs section. it is recommended that the clock input to the ADV7128 be driven by a ttl buffer (e.g., 74f244). 100 ire white level black level 17.61 0.66 0 0 ma v i out notes 1. outputs connected to a doubly terminated 75 w load. 2. v ref = 1.235v, r set = 560 w . 3. rs?43a levels and tolerances assumed on all levels. figure 3. i out video output waveform table i. video output truth table for the ADV7128 description i out 1 dac input data white level 17.62 3ff video video data video to black video data black level 0 00h note 1 typical with full scale = 17.62 ma. v ref = 1.235 v, r set = 560 w .
ADV7128 rev. 0 C6C reference input an external 1.23 v voltage reference is required to drive the ADV7128. the ad589 from analog devices is an ideal choice of reference. it is a two-terminal, low cost, temperature com- pensated bandgap voltage reference which provides a fixed 1.23 v output voltage for input currents between 50 m a and 5 ma. figure 4 shows a typical reference circuit connection dia- gram. the voltage reference gets its current drive from the ADV7128s v aa through an on-board 1 k w resistor to the v ref pin. a 0.1 m f ceramic capacitor is required between the comp pin and v aa . this is necessary so as to provide compensation for the internal reference amplifier. a resistance r set connected between r set and gnd deter- mines the amplitude of the output video level according to the following equation: i out (ma) = 7,969 v ref (v)/r set ( w ) (1) using a variable value of r set , as shown in figure 4, allows for accurate adjustment of the analog output video levels. use of a fixed 560 w r set resistor yields the analog output levels as quoted in the specification page. these values typically corre- spond to the rs-343a video waveform values as shown in figure 3. to dac v aa v ref gnd 1k w rset set r 560 w 500 w 100 w *additional circuitry, including decoupling components, excluded for clarity analog power plane comp 0.01 m f 5v + 5ma i ref ~ ~ ad589 (1.235v voltage reference) ADV7128 figure 4. reference circuit d/a converter the ADV7128 contains a 10-bit d/a converter. the dac is designed using an advanced, high speed, segmented architec- ture. the bit currents corresponding to each digital input are routed to either the analog output (bit = 1) or gnd (bit = 0) by a sophisticated decoding scheme. the use of identical current sources in a monolithic design guarantees monotonicity and low glitch. the on-board operational amplifier stabilizes the full-scale output current against temperature and power supply variations. analog output the analog output of the ADV7128 is a high impedance current source. the current output is capable of directly driving a 37.5 w load, such as a doubly terminated 75 w coaxial cable. figure 5a shows the required configuration for the output con- nected into a doubly terminated 75 w load. this arrangement will develop rs-343a video output voltage levels across a 75 w monitor. dac i out z o = 75 w (cable) z s = 75 w (source termination) z l = 75 w (monitor) figure 5a. analog output termination for rs-343a a suggested method of driving rs-170 video levels into a 75 w monitor is shown in figure 5b. the output current level of the dac remains unchanged, but the source termination resistance, z s , on the dac is increased from 75 w to 150 w . dac i out z o = 75 w (cable) z s = 150 w (source termination) z l = 75 w (monitor) figure 5b. analog output termination for rs-170 more detailed information regarding load terminations for vari- ous output configurations, including rs-343a and rs-170, is available in an application note entitled video formats & re- quired load terminations available from analog devices, publication no. e1228-15-1/89. figure 3 shows the video waveforms associated with the current output driving the doubly terminated 75 w load of figure 5a. gray scale operation the ADV7128 can be used for stand-alone, gray scale (mono- chrome) or composite video applications (i.e., only one channel used for video information). video output buffer the ADV7128 is specified to drive transmission line loads, which is what most monitors are rated as. the analog output configurations to drive such loads are described in the analog interface section and illustrated in figure 5. however, in some applications it may be required to drive long transmission line cable lengths. cable lengths greater than 10 meters can attenu- ate and distort high frequency analog output pulses. the inclu- sion of output buffers will compensate for some cable distortion. buffers with large full power bandwidths and gains between 2 and 4 will be required. these buffers will also need to be able to supply sufficient current over the complete output voltage swing. analog devices produces a range of suitable op amps for such applications. these include the ad84x series of monolithic op amps. in very high frequency applications (80 mhz), the ad9617 is recommended. more information on line driver buff- ering circuits is given in the relevant op amp data sheets. use of buffer amplifiers also allows implementation of other video standards besides rs-343a and rs-170. altering the gain components of the buffer circuit will result in any desired video level.
ADV7128 rev. 0 C7C dac z o = 75 w (cable) z s = 75 w (source termination) ad848 +v s 0.1 m f 0.1 m f i out 75 w 2 7 6 4 3 z 2 z l = 75 w (monitor) gain (g) = 1+ ? s z 1 z 1 z 2 figure 6. ad848 as an output buffer pc board layout considerations the ADV7128 is optimally designed for lowest noise perfor- mance, both radiated and conducted noise. to complement the excellent noise performance of the ADV7128 it is imperative that great care be given to the pc board layout. figure 7 shows a recommended connection diagram for the ADV7128. the layout should be optimized for lowest noise on the ADV7128 power and ground lines. this can be achieved by shielding the digital inputs and providing good decoupling. the lead length between groups of v aa and gnd pins should be minimized so as to minimize inductive ringing. ground planes the ADV7128 and associated analog circuitry, should have a separate ground plane referred to as the analog ground plane. this ground plane should connect to the regular pcb ground plane at a single point through a ferrite bead, as illustrated in figure 7. this bead should be located as close as possible (within 3 inches) to the ADV7128. the analog ground plane should encompass all ADV7128 ground pins, voltage reference circuitry, power supply bypass circuitry, the analog output traces and any output amplifiers. the regular pcb ground plane area should encompass all the digital signal traces, excluding the ground pins, leading up to the ADV7128. power planes the pc board layout should have two distinct power planes, one for analog circuitry and one for digital circuitry. the analog power plane should encompass the ADV7128 (v aa ) and all as- sociated analog circuitry. this power plane should be connected to the regular pcb power plane (v cc ) at a single point through a ferrite bead, as illustrated in figure 7. this bead should be lo- cated within three inches of the ADV7128. the pcb power plane should provide power to all digital logic on the pc board, and the analog power plane should provide power to all ADV7128 power pins, voltage reference circuitry and any output amplifiers. the pcb power and ground planes should not overlay portions of the analog power plane. keeping the pcb power and ground planes from overlaying the analog power plane will contribute to a reduction in plane-to-plane noise coupling. supply decoupling noise on the analog power plane can be further reduced by the use of multiple decoupling capacitors. (see figure 7.) optimum performance is achieved by the use of 0.1 m f ceramic capacitors. each of the two groups of v aa should be individually decoupled to ground. this should be done by placing the ca- pacitors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance. gnd rset i out ground ADV7128 c3 0.1 m f c5 0.1 m f z1 (ad589) r1 75 w c1 33 m f c2 10 m f comp c6 0.1 m f analog power plane v aa v ref l2 (ferrite bead) d0 d9 clock video output video data inputs analog ground plane c4 0.1 m f r set 560 w l1 (ferrite bead) cc +5v (v ) vendor part number fair-rite 274300111 or murata bl01/02/03 dale cmf-55c dale cmf-55c analog devices ad589jh component c1 c2 c3, c4, c5,c6 l1, l2 r1 r set z1 description 33 m f tantalum capacitor 10 m f tantalum 0.1 m f ceramic capacitor ferrite bead 75 w 1% metal film resistor 560 w 1% metal film resistor 1.235v voltage reference figure 7. ADV7128 typical connection diagram and component list
ADV7128 rev. 0 C8C c1760C24C1/93 printed in u.s.a. it is important to note that while the ADV7128 contains cir- cuitry to reject power supply noise, this rejection decreases with frequency. if a high frequency switching power supply is used, the designer should pay close attention to reducing power sup- ply noise. a dc power supply filter (murata bnx002) will pro- vide emi suppression between the switching power supply and the main pcb. alternatively, consideration could be given to using a three terminal voltage regulator. digital signal interconnect the digital signal lines to the ADV7128 should be isolated as much as possible from the analog outputs and other analog cir- cuitry. digital signal lines should not overlay the analog power plane. due to the high clock rates used, long clock lines to the ADV7128 should be avoided so as to minimize noise pickup. any active pull-up termination resistors for the digital inputs should be connected to the regular pcb power plane (v cc ), and not the analog power plane. analog signal interconnect the ADV7128 should be located as close as possible to the out- put connectors thus minimizing noise pickup and reflections due to impedance mismatch. the video output signals should overlay the ground plane, and not the analog power plane, thereby maximizing the high fre- quency power supply rejection. for optimum performance, the analog outputs should each have a source termination resistance to ground of 75 w (doubly ter- minated 75 w configuration). this termination resistance should be as close as possible to the ADV7128 so as to minimize reflections. additional information on pcb design is available in an applica- tion note entitled design and layout of a video graphics sys- tem for reduced emi. this application note is available from analog devices, publication number e1309-15-10/89. outline dimensions dimensions shown in inches and (mm). soic (r-28) pin 1 0.299 (7.60) 0.291 (7.40) 15 14 1 28 0.419 (10.65) 0.394 (10.00) 0.012 (0.32) 0.009 (0.23) 0.05 (1.27) 0.016 (0.40) 0.104 (2.65) 0.093 (2.35) 0.011 (0.30) 0.004 (0.10) 0.019 (0.49) 0.014 (0.35) 0.050 (1.27) bsc 0.712 (18.10) 0.697 (17.70)
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